include a ±5% tolerance on the actual value of the voltage and monotonic ramping of the supplies
during power-up. While it is not proven that ramping in a non-monotonic way would not work,
FPGAs are not tested that way after manufacturing, so it is better to guarantee a monotonic ramp in
order to avoid surprises. Devices also specify a minimum and a maximum ramping time for the
voltage rails. Again, this is just how they are tested after production, and it is very wise to follow these
guidelines.
An important aspect to bear in mind concerns in-rush current at power-up due to the decoupling
capacitors on the power supply rails. If C is the total capacitance, I
c
= C*ΔV/ΔT, so one might want to
slow the ramping process down using a soft-start circuit in order to avoid the kick-in of protection
mechanisms in regulators, which could in turn compromise monotonicity.
Sequencing of supply voltages, i.e., making one available, then another one and so on, was a
required practice in old technologies, and nowadays it is only recommended. It seems sensible that the
I/O stages get power only after the internal logic is properly configured. A Supply Voltage Supervisor
(SVS) chip can be used to control the process. Sequencing is also good to make sure that the main
(typically 5 V) rail feeding the regulators is well established (i.e., all capacitors charged) before they
begin requesting current from it. Otherwise the 5 V protection could trip and spikes could appear in
the output of the regulators.
The design of a proper bypassing network using capacitors is also a critical issue. A decoupling
network should look like a short to ground for all the frequencies of power supply noise we want to
reject. At high frequencies, like the ones of interest for this discussion, a capacitor chip can be
modelled as an equivalent RLC circuit to take into account the various imperfections in its design. The
parasitic inductance dominates at high frequencies, and is (almost) exclusively determined by the
package type of the capacitor. The global frequency response presents a downward slope at low
frequencies whose value depends on the capacitance, and an upward slope at high frequencies whose
value depends on the parasitic inductance. The minimum of the curve thus depends on the capacitance
value, and can be made arbitrarily wide by selecting a suitable set of capacitor values and placing them
in parallel. High-value capacitors take care of low-frequency perturbations and can be placed
relatively far away from the chip, while low values of capacitance (typically 10 nF), can be placed
close to the chip — ideally below it — to take care of the fast perturbations. Reference [6] can be
consulted for further details.
6.3 Interfacing to the outside world
Modern FPGAs have very versatile I/O blocks which make them easy to interface to other chips. In
this section, we look in particular at issues which could appear when interfacing to Analog to Digital
Converters (ADCs) or DACs.
Whenever a design deals with high-speed, high-pin-count parallel busses, as is the case often
when interfacing FPGAs and ADCs/DACs, there is potential for noise problems. This is because the
I/O drivers in the FPGAs commute state all at the same time, creating large current surges in the
Power Distribution System (PDS). The PDS should be well decoupled using the appropriate mix of
capacitors as discussed above, but it cannot filter all the noise at all frequencies. In addition, sampling
many bits at a high frequency can pose synchronization problems. If the clock edge is very close to the
transition of any of the data bits, a problem known as metastability — to be explained later — can
arise. It is therefore desirable to avoid simultaneous fast-switching of large busses if possible. One
example where this is possible is in the sampling of high frequency, low bandwidth analog signals.
According to sampling theory, there is no need to sample them in their main Nyquist zone, i.e., with at
least twice their frequency. It is sufficient to sample them at least faster than twice their bandwidth –
which can be significantly slower. This can be a solution for systems where latency is more or less a
secondary concern, but it might not be possible for feedback systems. Another possibility for
mitigating noise problems is to choose ADC and DAC chips which use differential signalling for the